Examination review questions



a) Briefly describe the differences between a microprocessor’s interface bus, a

system I/O bus (such as PCI), and a peripheral interface. Consider the

bandwidth characteristics and physical implementation of each.


b) Show how four 64Mbit byte-wide DRAM chips could be interfaced to a simple

32- bit microprocessor. Give a schematic diagram showing the connections, and

a timing diagram to demonstrate the operation of the control signals.


 c) Why might accesses to sequential DRAM addresses be treated differently from non-sequential ones?


d)  Why do pipelines exhibit branch and load delays?


e) What impact does pipeline length have on clock frequency?


f) Why might a shorter pipeline result in a more power-efficient design?


g) Recently we have seen microprocessor manufacturers release dual-processor

chips where each processor has a shorter pipeline than the earlier single processor per chip designs. What sort of applications might run better on

the older chips and vice versa?


h) What is a data cache and why is it vital for high performance processors?


i) What is a cache line and how big is it likely to be?